Cadence OrCAD PCB design suites combine industry-leading, production-proven, and highly scalable PCB design applications to deliver complete schematic entry, simulation, and place-and-route solutions. With these powerful, intuitive tools that integrate seamlessly across the entire PCB design flow, engineers can quickly move products from conception to final output.
To stay competitive in today’s market, companies must move their designs from engineering to manufacturing within ever-shrinking design schedules. Available as standalone products or in comprehensive suites, Cadence OrCAD personal productivity tools have a long
history of addressing PCB design challenges, whether simple or complex. The powerful, tightly integrated PCB design technologies include OrCAD Capture for schematic design, various librarian tools, OrCAD PCB Editor for place and route, PSpice A/D for circuit
simulation, OrCAD PCB SI for signal integrity analysis, and SPECCTRA for OrCAD for automatic routing. Easy to use and intuitive, these tools bring exceptional value and future-proof scalability to the Cadence Allegro system interconnect design platform to grow with future design demands. OrCAD PCB design suites provide integrated front-end design and simulation technology (Cadence OrCAD EE Designer) as well as an integrated back-end place-and-route design solution (Cadence OrCAD PCB Designer) to boost productivity and accelerate time to market.
DATE: 05-18-2012 HOTFIX VERSION: 022
CCRID PRODUCT PRODUCTLEVEL2 TITLE
686560 CAPTURE BACKANNOTATE Changing pin group property after pin swap resets pin numbers
740162 ALLEGRO_EDITOR EDIT_ETCH Enhance Allegro PCB Editor use model when adding NULL net copper
963645 PSPICE MODELEDITOR Model import wizard crashes while associating IRF150 to schematic symbol.
966422 CAPTURE PROPERTY_EDITOR References changes, done in the property editor, lost on closing and reopening the design
968674 PSPICE PROBE Display Measurement evaluation does not show Measurement and its value directly.
970281 CAPTURE ANNOTATE Annotation assigns wrong refdes to resistor.
975497 CAPTURE NETLIST_OTHER Capture crashes while trying to generate other format netlist
993129 CONCEPT_HDL CONSTRAINT_MGR unable to select multiple nets in schematic and highlighted them in CM
997518 PSPICE PROBE Mouse click on probe window is required to see Plots after simulation for multiple plots on win 7
999603 CAPTURE NETGROUPS Capture crashes on trying to rename a netgroup member.
1001167 SIG_INTEGRITY GEOMETRY_EXTRACT Need warning message of DC shape check.
1002370 ALLEGRO_EDITOR SKILL Allegro axlMeterIsCancelled function not always returning t when Stop button is selected.
1003205 APD DATABASE Fillet gone after DB doctor check
1003447 SIP_LAYOUT DIE_EDITOR Rounding errors are causing problems for shrunk dies with .001 u mfg grid
1003821 ALLEGRO_EDITOR EDIT_ETCH Diff pair routing starts from unexpacted pin for non control cline
1005793 ALLEGRO_EDITOR DRC_CONSTR Update DRC with Multi-thread DRC changes DRC without any change in design for Win 7 OS
1005835 ALLEGRO_EDITOR OTHER Display Status fails to show rats on missing connection point
1006701 ALLEGRO_EDITOR SHAPE Shape to shape void incorrect spacing value in L3 layer.
1006718 CONSTRAINT_MGR OTHER Allegro crashes while sliding nets having custom formula in CMGR
1006920 CONCEPT_HDL CORE Global Navigate hangs schematic
1007102 CAPTURE OTHER Latest release on START page is not getting updated
1008585 ALLEGRO_EDITOR MANUFACT Manufacturing X Section Chart layer is not coming up correctly in this design
1009047 F2B PACKAGERXL Packager crashes after installing ISR s19
1009443 ALLEGRO_EDITOR DRAFTING Pressing TAB key in Dimension environment results error: E- (SPMHA2-65): Error -3000314.
1009562 CAPTURE TCL_INTERFACE Library correction TCL utility is failiing to correct the corrupt libraries.
1009941 SIP_LAYOUT DIE_ABSTRACT_IF Distributed DIE abstract generated from Virtuoso VSiP Architect has errors on Shapes used in Area xfer
1010201 ALLEGRO_EDITOR INTERACTIV dbdoctor on psm file returns error in open drawing
1010432 ALLEGRO_EDITOR SYMBOL Error in placing Pin in Symbol editor, "W- (SPMHDB-226): Inconsistent rotation data."
1010512 ALLEGRO_EDITOR DRC_CONSTR Can not check short pin in DRC
1010611 MODEL_INTEGRIT TRANSLATION Translation failed due to IBIS2DML errors.
1011022 ALLEGRO_EDITOR OTHER Create Fanout crashes allegro if dimension is visible
About Cadence Design Systems, Inc.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.